Paper | Title | Other Keywords | Page |
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THAFP11 | FPGA-Based Digital IQ Demodulator Used in the Beam Position Monitors for HIAF BRing | electron, synchrotron, electronics, pick-up | 429 |
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Funding: NSFC No. E911010301, Y913010GJ0, A digital beam position monitor processor has been developed for the High Intensity heavy ion Accelerator Facility (HIAF). The digital IQ demodulator is used in the Beam Position Monitor (BPM) signal processing. All data acquisition and digital signal processing algorithm routines are performed within the FPGA. In the BPM electronics system, a 250 MHz sample rates ADC was used to digitize the pick-ups signal. In the FPGA, the digital signal is filtered by ultra-narrow bandpass filters, then the digital IQ demodulator is used to calculate the beam position with difference-over-sum algorithm. The heavy ion synchrotron CSRm revolution frequency is changing from 0.2 MHz to 1.78 MHz when accelerates charged particles. In this design, a Direct Digital Synthesizer (DDS) whose output frequency changes over time is applied to generate the in-phase and quadrature components in the digital IQ demodulator. The performance of this designed BPM processor was evaluated with the online HIRFL-CSRm. |
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Slides THAFP11 [1.332 MB] | |||
Poster THAFP11 [4.534 MB] | |||
DOI • | reference for this paper ※ doi:10.18429/JACoW-HB2023-THAFP11 | ||
About • | Received ※ 28 September 2023 — Revised ※ 05 October 2023 — Accepted ※ 10 October 2023 — Issued ※ 19 October 2023 | ||
Cite • | reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml) | ||