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RIS citation export for THAFP11: FPGA-Based Digital IQ Demodulator Used in the Beam Position Monitors for HIAF BRing

TY  - CONF
AU  - Ni, F.F.
AU  - Li, Z.X.
AU  - Tian, R.X.
AU  - Wei, Y.
AU  - Wu, J.X.
ED  - Cai, Yunhai
ED  - Nagaitsev, Sergei
ED  - Kim, Dong Eon
ED  - Marx, Michaela
ED  - Schaa, Volker R. W.
TI  - FPGA-Based Digital IQ Demodulator Used in the Beam Position Monitors for HIAF BRing
J2  - Proc. of HB2023, Geneva, Switzerland, 09-13 October 2023
CY  - Geneva, Switzerland
T2  - ICFA Advanced Beam Dynamics Workshop on High-Intensity and High-Brightness Hadron Beams
T3  - 68
LA  - english
AB  - A digital beam position monitor processor has been developed for the High Intensity heavy ion Accelerator Facility (HIAF). The digital IQ demodulator is used in the Beam Position Monitor (BPM) signal processing. All data acquisition and digital signal processing algorithm routines are performed within the FPGA. In the BPM electronics system, a 250 MHz sample rates ADC was used to digitize the pick-ups signal. In the FPGA, the digital signal is filtered by ultra-narrow bandpass filters, then the digital IQ demodulator is used to calculate the beam position with difference-over-sum algorithm. The heavy ion synchrotron CSRm revolution frequency is changing from 0.2 MHz to 1.78 MHz when accelerates charged particles. In this design, a Direct Digital Synthesizer (DDS) whose output frequency changes over time is applied to generate the in-phase and quadrature components in the digital IQ demodulator. The performance of this designed BPM processor was evaluated with the online HIRFL-CSRm.
PB  - JACoW Publishing
CP  - Geneva, Switzerland
SP  - 429
EP  - 432
KW  - electron
KW  - FPGA
KW  - synchrotron
KW  - electronics
KW  - pick-up
DA  - 2024/04
PY  - 2024
SN  - 2673-5571
SN  - 978-3-95450-253-0
DO  - doi:10.18429/JACoW-HB2023-THAFP11
UR  - https://jacow.org/hb2023/papers/thafp11.pdf
ER  -